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CXP888P60
CMOS 8-bit Single Chip Microcomputer
Description The CXP888P60 is a CMOS 8-bit micro-computer which consists of A/D converter, serial interface, timer/counter, time base timer, high precision timing pattern generation circuits, PWM output, VISS/ VASS circuit, 32kHz timer/counter, remote control receiving circuit, VSYNC separator and the measurement circuit which measure signals of capstan FG amplifier and drum FG/PG amplifier and other servo systems, as well as basic configurations like 8-bit CPU, PROM, RAM and I/O port. They are integrated into a single chip. Also, CXP888P60 provides sleep/stop function which enables to lower power consumption. The CXP888P60 is the PROM-incorporated version of the CXP88860 with built-in mask ROM. This provides the additional feature of being able to write directly into the program. Thus, it is most suitable for evaluation use during system development and for small-quantity production. 100 pin QFP (Plastic)
Structure Silicon gate CMOS IC
Features * A wide instruction set (213 instructions) which cover various types of data -- 16-bit arithmetic/multiplication and division/boolean bit operation instructions * Minimum instruction cycle 250ns at 16MHz operation 122s at 32kHz operation * Incorporated PROM capacity 60K bytes * Incorporated RAM capacity 1600 bytes (including PPG RAM) * Peripheral function -- A/D converter 8 bits, 8 channels, successive approximation system (Conversion time of 20s/16MHz) -- Serial interface Incorporated 8-bit, 8-stage FIFO for data (Auto transfer for 1 to 8 bytes), 1 channel 8-bit clock sync type, 1 channel -- Timer 8-bit timer/counter, 2 channels 19-bit time base timer 32kHz timer/counter -- High precision timing pattern generation PPG 19 pins 32-stage programmable circuit RTG 5 pins, 1 channel 5-bit, 8-satge FIFO (RECCTL control), 1channel -- PWM/DA gate output 12 bits, 2 channels (Repetitive frequency 62.5kHz/16MHz) DA gate pulse output, 13 bits, 2 channels -- Analog signal input circuit Capstan FG amplifier circuit Drum FG amplifier circuit Drum PG amplifier circuit PBCTL amplifier circuit -- CTL write/rewrite circuit Recording current control circuit -- Servo input control Capstan FG, Drum FG/PG, CTL input -- VSYNC separator -- FRC capture unit Incorporated 26-bit and 8-stage FIFO -- PWM output 14-bit, 1 channel -- VISS/VASS circuit Pulse duty auto detection circuit -- 32kHz timer/event counter 32kHz oscillation circuit, ultra-low speed instruction mode -- Remote control reception circuit 8-bit pulse measurement counter, 6-stage FIFO -- Tri-state output PPG 1 pin, output 8 pins -- Pseudo HSYNC output function -- High speed head switching circuit * Interruption 20 factors, 15 vectors, multi-interruption possible * Standby mode SLEEP/STOP * Package 100-pin plastic QFP
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
E96107-ST
Block Diagram
AVREF AVss INT0 INT1/NMI INT2 EXTAL XTAL TEX TX RST MP VDD Vss Vpp
AVDD
2
PORT A
AN0 to AN13 8 PA0 to PA7 SPC700 CPU CORE
PORT B
14 CLOCK GENERATOR/ SYSTEM CONTROL 8 PB0 to PB7
A/D CONVERTER
2
NMI
CS0 SI0 SO0 SCK0 FIFO
SERIAL INTERFACE UNIT (CH0)
EC
8 BIT TIMER/COUNTER 0
INTERRUPT CONTROLLER
2
PROM 60K BYTES
RAM 1600 BYTES
PORT C
SI1 SO1 SCK1 8
SERIAL INTERFACE UNIT (CH1)
PC0 to PC7
TO
SYNC 2 2 PRESCALER/ TIME BASE TIMER 3 FIFO FRC CAPTURE UNIT FIFO
PORT E
V SYNC SEPARATOR
PORT D
EC SELECT
8 BIT TIMER/COUNTER1
8
PD0 to PD7
4 4
PORT F
PE0, 1, 6, 7 PE2 to PE5 4 4 PF0 to PF3 PF4 to PF7
EXI0 EXI1 SERVO INPUT CONTROL
CFG DFG DPG CTLAMP
GAIN CONTROL AMP
32kHz TIMER/COUNTER
PWM
14 BIT PWM GENERATOR 2 2 PROGRAMABLE PATTERN GENERATOR RAM CH0 REALTIME PULSE GENERATOR CH1 FIFO 5
PORT I
PORT H
DDO
VISS/VASS
PULSE WIDTH COUNTER
PORT G
AMPVDD
AMPVSS
PPO0 to PPO18
RTO3 to RTO7
-2-
4 19 5
RMC
REMOCON INPUT
2
PG0, 1
8
PH0 to PH7
PWM0 DAA0
12 BIT PWM GENERATOR CH0
8
PI0 to PI7
PWM1 DAA1
12 BIT PWM GENERATOR CH1
HGO
PSEUDO HSYNC GENERATOR
2
ADJ RECCTL CTLCIN
CTL R/W CONTROL
CXP888P60
CXP888P60
Pin Assignment (Top View)
PA0/PPO0/HGO
PB6/PPO14
PB7/PPO15
PA1/PPO1
PE3/SYNC
PA7/PPO7
PA2/PPO2
PA3/PPO3
PA4/PPO4
PA5/PPO5
PA6/PPO6
PE0/SCK1
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 PB5/PPO13 PB4/PPO12 PB3/PPO11 PB2/PPO10 PB1/PPO9 PB0/PPO8 PC7/RTO7 PC6/RTO6 PC5/RTO5 PC4/RTO4 PC3/RTO3 PC2/PPO18 PC1/PPO17 PC0/PPO16 PI7 PI6 PI5 PI4 PI3 PI2 PI1/EC/INT2 PI0/INT0/ENV-DET PD7/SI0 PD6/SO0 PD5/SCK0 PD4/CS0 PD3/TO/DDO/ADJ/SRVO PD2/PWM PD1/RMC PD0/INT1/NMI 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PE5/EXI1 PE6/PWM0/DAA0 PE7/PWM1/DAA1 CFG DFG DPG VREFOUT AMPVSS CTLSAMPI CTLFAMPO CTLAG CTLAMP (+) CTLAMP (-) CTLCIN (-) CTLCIN (+) RECCTL (+) RECCTL (-) AMPVDD RECCAP VDD AN0/ANOUT AN1 AN2 AN3 PF0/AN4 PF1/AN5 AVDD AVREF AVSS PF2/AN6
PH5
PG1/AN13
PG0/AN12
PF7/AN11
PF6/AN10
PH7
PH6
EXTAL
XTAL
RST
PH2
PH1
PH0
VSS
MP
PE2/SI1
Note) 1. Vpp (Pin 90) is always connected to VDD. 2. VDD (Pins 61 and 89) are both connected to VDD 3. Vss (Pins 41 and 88) are both connected to GND. 4. MP (Pin 39) must be connected to GND. -3-
PF5/AN9
PF4/AN8
PF3/AN7
PH4
PH3
PE4/EXI0
Vpp
VDD
VSS
TX
TEX
PE1/SO1
CXP888P60
Pin Description Symbol PA0/PPO0 /HGO PA1/PPO1 to PA7/PPO7 I/O Output/Real-time output/Output Output/ Real-time output (Port A) 8-bit output port. Data is gated with PPO contents by OR-gate and they are output. (8 pins) (Port B) 8-bit output port. Data is gated with PPO contents by OR-gate and they are output. Tri-state control is possible. (8 pins) (Port C) 8-bit I/O port. I/O can be set in a unit of single bits. Data is gated with PPO or RT contents by OR-gate and they are output. (8 pins) Description Pseudo HSYNC output pin.
PB0/PPO8 to PB7/PPO15
Output/ Real-time output
Programmable pattern generator (PPG) output. Functions as high precision realtime pulse output port. (19 pins) PA0 can be tri-state controlled with PPG.
PC0/PPO16 to PC2/PPO18 PC3/RTO3 to PC7/RTO7 PD0/INT1/ NMI PD1/RMC PD2/PWM PD3 /TO DDO/ADJ SRVO PD4/CS0 PD5/SCK0 PD6/SO0 PD7/SI0 PE0/SCK1 PE1/SO1 PE2/SI1 PE3/SYNC PE4/EXI0 PE5/EXI1 PE6/PWM0/ DAA0 PE7/PWM1/ DAA1
I/O/ Real-time output
I/O/ Real-time output
Real-time pulse generator (RTG) output. Functions as high precision real-time pulse output port. (5 pins) Input pin to request external interruption and non-maskable interruption. Remote control receiving circuit input pin. 14-bit PWM output pin. Timer/counter, CTL duty detector, 32kHz oscillation adjustment and servo amplifier output pin. Serial chip select (CH0) input pin. Serial clock (CH0) I/O pin. Serial data (CH0) output pin. Serial data (CH0) input pin. Serial clock (CH1) I/O pin Serial data (CH1) output pin
I/O/Input/Input I/O/Input I/O/Output I/O/Output/Output/ (Port D) 8-bit I/O port. I/O can be Output/Output set in a unit of single bits. (8 pins) I/O/Input I/O/I/O I/O/Output I/O/Input Output/I/O Output/Output Input/Input Input/Input Input/Input Input/Input Output/Output Output/Output -4-
Serial data (CH1) input pin (Port E) 8-bit port. Bits 2, 3, 4 and 5 Composite sync signal input pin. are for inputs; bits 0, 1, 6 and 7 are for outputs. External input pin for FRC capture unit. (8 pins) (2 pins) DA gate pulse output pin. (2 pins)
PWM output pin. (2 pins)
CXP888P60
Description AN0/ANOUT AN1 to AN3 PF0/AN4 to PF3/AN7 PF4/AN8 to PF7/AN11 PG0/AN12 PG1/AN13
I/O Input/Output Input Input/Input
Description Analog circuit internal waveform output pin.
Output/Input
(Port F) Lower 4 bits are for inputs; upper 4 bits are for outputs. Lower 4 bits are standby release input pins. (8 pins) (Port G) 2-bit input port. (2 pins)
Analog input pin for A/D converter. (14 pins)
Input/Input
PH0 to PH7
Output
(Port H) 8-bit output port; N-ch open drain output of medium drive voltage (12V) and large current (12mA). (8 pins) (Port I) 8-bit I/O port. I/O can be set in a unit of single bits. Function as standby release input can be set in a unit of single bits. (8 pins) Input pin to request Trigger pulse input external interruption. pin for head Active when falling switching. edge. Input pin to request External event input external interruption. pin for timer/counter. Active when falling edge.
PI0/INT0/ ENV-DET
I/O/Input
PI1/EC/ INT2 PI2 to PI7 CFG DFG DPG RECCTL (+) RECCTL (-) CTLCIN (+) CTLCIN (-) CTLAMP (+) CTLAMP(-) CTLFAMPO CTLSAMPI RECCAP VREFOUT CTLAG AMPVSS AMPVDD
I/O/Input/Input
I/O Input Input Input I/O Output Input Output Input I/O Output Output Capstan FG input pin. Drum FG input pin. Drum PG input pin. RECCTL signal output pin. (2 pins) PBCTL signal input pin. (2 pins)
Connected to RECCTL (+) and RECCTL (-) with the internal switch for playback. (2 pins) Input PBCTL signal with capacitor coupled. (2 pins) PBCTL signal 1st amplifier output. PBCTL signal 2nd amplifier input. Capacitor connecting pin for the slope setting of the CTL writing trapezoidal wave. Capacitor connecting pin for the VREF level smoothing of DPG, DFG and CFG. Capacitor connecting pin for the CTL and AGND smoothing. Analog signal input circuit GND pin. Analog signal input circuit power supply pin.
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CXP888P60
Symbol EXTAL XTAL TEX TX RST MP AVDD AVREF AVSS VDD Vpp VSS Input Input Output Input Output Input Input
I/O
Description Connecting pin of crystal oscillator for system clock. When supplying the external clock, input it to EXTAL pin and input the opposite phase clock to XTAL pin. Connecting pin of crystal oscillator for 32kHz timer clock. When used as event counter, input to TEX pin and leave TX pin open. (In this time, feedback resistor is not removed.) System reset pin; Low level active. Test mode input pin. Always connect to GND. Positive power supply pin for A/D converter. Reference voltage input pin for A/D converter. GND pin for A/D converter. Positive power supply pin. Positive power supply for incorporated PROM writing. Connect this pin to VDD for normal operation. GND pin. Connect both Vss pins to GND.
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CXP888P60
Input/Output Circuit Formats for Pins Pin Port A Circuit format When reset
PA0/PPO0/ HGO 1 pin
Data bus
HOUT PPO0 PA0
MPX
Hi-Z
RD (Port A)
HSEL HOUTE
MPX
Output becomes active from high impedance by data writing to port. PPO1 PPG control status register bit 0 Tri-state control selection PPO1
PA1/PPO1 1 pin
Data bus
PA1
Hi-Z
RD (Port A) Output becomes active from high impedance by data writing to port.
Port A
PPO data
PA2/PPO2 to PA7/PPO7
Data bus
Port A data
Hi-Z
RD (Port A)
6 pins Port B
RTO data
Output becomes active from high impedance by data writing to port.
PB0/PPO8 to PB7/PPO15
Port B data Data bus RD (Port B) Port B tri-state control
Hi-Z
8 pins
-7-
CXP888P60
Pin Port C PC0/PPO16 to PC2/PPO18 PC3/RTO3 to PC7/RTO7
PPO, RTO data Port C data
Circuit format
When reset
Input protection circuit Port C direction IP Data bus RD (Port C)
Hi-Z
8 pins
RD (Port C direction)
Port D
Port D data
PD0/INT1/ NMI PD1/RMC PD4/CS0 PD7/SI0
Port D direction IP RD (Port D) PD1...Remote control circuit PD0...Interruption circuit PD4, 7...Serial CH0 Schmitt input
Hi-Z
Data bus
4 pins
Port D
Port D function select
PD2/PWM PD3/TO/ DDO/ADJ/ SRVO
PD2 ... 14-bit PWM PD3 ... Timer/counter, CTL duty detection circuit, 32kHz timer, amplifier circuit Port D data Port D direction
MPX
Hi-Z
IP Data bus RD (Port D)
2 pins
-8-
CXP888P60
Pin Port D
Port D function select
Circuit format
When reset
PD5/SCK0 PD6/SO0
Port D data
SI0 CH0
MPX
Hi-Z
MPX Note) PD5 is schmitt input PD6 is inverter input IP
Port D direction
Data bus
2 pins Port E
RD (Port D) SI0, CH0
Port/SCK output select
PE0/SCK1
SI0 CH1 MPX Port E data
Hi-Z
Hi-Z control Data bus SI0 CH1 RD (Port E)
IP
1 pin Port E
Port E function select
PE1/SO1
SI0 CH1 Port E data MPX
Hi-Z
Data bus
Hi-Z control RD (Port E)
1 pin Port E PE2/SI1 PE3/SYNC PE4/EXI0 PE5/EXI1
Schmitt input IP PE2...SI0 CH1 PE3 PE4 Servo input PE5 Data bus RD (Port E)
Hi-Z
4 pins
-9-
CXP888P60
Pin Port E
Port/DA/PWM select
Circuit format
When reset
PE6/PWM0/ DAA0 PE7/PWM1/ DAA1
DA gate output or PWM output
MPX
High level
Port E data
Data bus Hi-Z control
2 pins Port E
RD (Port E)
Input multiplexer
AN0/ANOUT
IP
A/D converter
Hi-Z
From amplifier circuit Analog output control
1 pin AN1 to AN3 3 pin Port F
Input multiplexer
Input multiplexer IP A/D converter
Hi-Z
PFO/AN4 to PF3/AN7
IP
A/D converter
Hi-Z
Data bus
4 pins Port F
RD (Port F)
PF4/AN8 to PF7/AN11
Port F data
Data bus RD (Port F) Port/AD select
IP
Hi-Z
A/D converter Input multiplexer
4 pins
- 10 -
CXP888P60
Pin Port G PG0/AN12 to PG1/AN13
Circuit format
Input multiplexer IP A/D converter
When reset
Hi-Z
Data bus
2 pins Port H PH0 to PH7
Port H data
RD (Port G)
Medium drive voltage12 V
Hi-Z
Large current 12mA
Data bus
8 pins
RD (Port H)
Port I
Port I data
PI0/INT0/ EVN-DET to PI1/EC/INT2
Port I direction IP
Data bus RD (Port I) Standby release Interruption circuit Data bus Edge detection
Hi-Z
2 pins
RD (Port I direction)
Port I
Port I data
PI2 to PI7
Data bus
Port I direction IP RD (Port I) Standby release Data bus
Hi-Z
Edge detection
6 pins
RD (Port I direction)
- 11 -
CXP888P60
Pin
Circuit format
When reset
CTLAMP (+) CTLAMP (-) CTLFAMPO
CTLAG CTLAMP (+) IP
1/2AMPVDD
CTLFAMPO
IP CTLAMP (-)
3 pins
Input pin charge control
CTLSAMPI
Input pin charge control IP LPF circuit CTLAG
1/2AMPVDD
1 pin
CFG DFG DPG
Input pin charge control IP LPF circuit VREFOUT
1/2AMPVDD
3 pins
AMPVDD
CTLAG VREFOUT
IP AMPVSS VREFOUT... CFG, DFG, DPG amplifiers CTLAG........ CTL amplifier
1/2AMPVDD
2 pins
- 12 -
CXP888P60
Pin
Circuit format
AMPVDD Recording current control circuit
When reset
Write current select RTO6
RECCTL (+)
IP RTO7 RTO3 AMPVSS CTLCIN (+) pin
Hi-Z
1 pin
RTG control permission
AMPVDD Recording current control circuit
Write current select RTO7
RECCTL (-)
IP RTO6 RTO3 AMPVSS CTLCIN (-) pin
Hi-Z
1 pin
RTG control permission
From RECCTL (+) pin
IP
CTLCIN (+)
RTO3 RTG control permission
Hi-Z
1 pin
AMPVSS
CTLCIN (-)
From RECCTL (-) pin RTO3 RTG control permission
IP
Hi-Z
1 pin
AMPVSS
RTG control permission
RECCAP
RTO5 IP
Low level
1 pin
Recording current control circuit
- 13 -
CXP888P60
Pin
Circuit format
* Shows the circuit composition during oscillation. * Feedback resistor is removed and XTAL becomes High level during stop. XTAL
When reset
EXTAL XTAL
EXTAL
IP
Oscillation
2 pins
TEX TX
32kHz timer/ counter TEX IP
* Shows the circuit composition during oscillation. * Feedback resistor is removed during 32kHz oscillation circuit stop by software. At this time, TEX pin outputs Low level and TX pin outputs High level.
Oscillation
2 pins
TX
Pull-up resistor
RST
IP
Schmitt input
Low level
Power-on-reset circuit
1 pin
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CXP888P60
Absolute Maximum Ratings Item Symbol VDD Vpp AVDD Supply voltage AVSS Rating -0.3 to +7.0 -0.3 to +13 AVss to +7.0 1 -0.3 to +0.3 Unit V V V V V V V V V mA mA mA mA mA C C mW Port PH
(Vss = 0V reference) Remarks
Incorporated PROM
AMPVDD AMPVSS to +7.0 2 AMPVSS Input voltage Output voltage Medium drive output voltage High level output current High level total output current VIN VOUT VOUTP IOH IOH IOL Low level output current IOLC Low level total output current Operating temperature Storage temperature Allowable power dissipation IOL Topr Tstg PD 20 130 -10 to +75 -55 to +150 600 -0.3 to +0.3 -0.3 to +7.0 3 -0.3 to +7.0 3 -0.3 to +15.0 -5 -50 15
Total of output pins Other than large current output ports (value per pin) Large current output port 4 (value per pin) Total of output pins
QFP package type
1) AVDD and VDD must not exceed +0.3V. 2) AMPVDD and VDD must not exceed +0.3V. 3) VIN and VOUT must not exceed VDD +0.3V. 4) The large current output port is port H (PH). Note) Usage exceeding absolute maximum ratings may permanently impair the LSI. Normal operation should better take place under the recommended operating conditions. Exceeding those conditions may adversely affect the reliability of the LSI.
- 15 -
CXP888P60
Recommended Operating Conditions Item Symbol Min. 4.5 3.5 2.7 2.5 Vpp Analog power supply AVDD AMPVDD VIH High level input voltage VIHS VIHTS VIHEX VIL Low level input voltage VILS VILTS VILEX Operating temperature 1) 2) 3) 4) Topr Max. 5.5 5.5 5.5 5.5 V Unit Remarks
(Vss = 0V)
Guaranteed operation range for 1/2 and 1/4 frequency dividing clock Guaranteed operation range for 1/16 frequency dividing clock or during SLEEP mode Guaranteed operation range by TEX clock Guaranteed data hold operation range during STOP 1 2 3 CMOS schmitt input 4 TTL schmitt input 5 EXTAL pin6 3 TEX pin7
VDD Supply voltage
Vpp = VDD 4.5 4.5 0.7VDD 0.8VDD 2.2 5.5 5.5 VDD VDD VDD V V V V V V V V V V C
VDD - 0.4 VDD + 0.3 0 0 0 -0.3 -10 0.3VDD 0.2VDD 0.8 0.4 +75
CMOS schmitt input 4 TTL schmitt input 5 EXTAL pin 6 TEX pin 7
AVDD and VDD should be set to the same voltage. AMPVDD and VDD should be set to the same voltage. Normal input port (each pin of PC, PD2, PD3, PD6, PF0 to PF3, PG and PI2 to PI7), MP pin Each pin of RST, PD0/INT1/NMI, PD1/RMC, PD4/CS0, PD5/SCK0, PD7/SI0, PE0/SCK1, PE2/SI1, PE3/SYNC, PE4/EXI0, PE5/EXI1, PI0/INT0, PI1/EC/INT2 (For PE3/SYNC, when CMOS schmitt input is selected with mask option.) 5) PE3/SYNC 6) Specifies only during external clock input. 7) Specifies only during external event input.
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CXP888P60
Electrical Characteristics DC Characteristics (VDD = 4.5 to 5.5V) Item High level output voltage Symbol Pins PA to PD, PE0 to PE1, PE6 to PE7, PF4 to PF7, PH (VOL only) PI RST1 (VOL only) PD, PH IIHE IILE Input current IIHT IILT IILR I/O leakage current Open drain output leakage current (N-CH Tr off state) IIZ RST PA to PG, PI, MP, AN0 to AN3, TEX EXTAL Conditions VDD = 4.5V, IOH = -0.5mA VDD = 4.5V, IOH = -1.2mA VDD = 4.5V, IOL = 1.8mA VDD = 4.5V, IOL = 3.6mA VDD = 4.5V, IOL = 12.0mA VDD = 5.5V, VIH = 5.5V VDD = 5.5V, VIL = 0.4V VDD = 5.5V, VIH = 5.5V VDD = 5.5V, VIL = 0.4V VDD = 5.5V, VI = 0, 5.5V 0.5 -0.5 0.1 -0.1 -1.5 (Ta = -10 to +75C, Vss = 0V reference) Min. 4.0 3.5 0.4 0.6 1.5 40 -40 10 -10 -400 10 Typ. Max. Unit V V V V V A A A A A A
VOH
Low level output voltage
VOL
ILOH
PH
VDD = 5.5V VOH = 12V 16MHz crystal oscillation (C1 = C2 = 15pF) VDD = 5.5V3 SLEEP mode VDD = 5.5V 2.0 35
50
A
IDD1
45
mA
IDDS1
8
mA
Supply current2
IDD2
32kHz crystal oscillation (C1 = C2 = 47pF) VDD, VSS VDD = 3.3V SLEEP mode VDD = 3V 0.3V 9 35 A 50 100 A
IDDS2
IDDS3
STOP mode (EXTAL and TEX pins oscillation stop) VDD = 5V0.5V
PC, PD, PE0, PE2 to PE5 PF, PG, PI, RECCTL (+), RECCTL (-), Clock 1MHz CTLAMP (+), 0V other than the measured pins CTLAMP (-), CTLSAMPI, CFG, DFG, DPG
30
A
Input capacity
CIN
10
20
pF
1) RST pin specifies the low level input voltage only when the power-on-reset circuit is selected. 2) When entire output pins are open. 3) When setting upper 2 bits (CPU clock selection) of clock control register (CLC: 00FEH) to "00" and operating in high speed mode (1/2 frequency dividing clock). - 17 -
CXP888P60
AC Characteristics (1) Clock timing Item System clock frequency System clock input pulse width System clock input rise and fall times Event count clock input pulse width Event count clock input rise and fall times System clock frequency Event count clock input pulse width Event count clock input rise and fall times 1) Symbol fC Pin
(Ta = -10 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Condition Fig. 1, Fig. 2 Fig. 1, Fig. 2 External clock drive Fig. 1, Fig. 2 External clock drive Fig. 3 Fig. 3 VDD = 2.7 to 5.5V Fig. 2 (32kHz clock applied condition) Fig. 3 Fig. 3 10 20 Min. 1 28 200 Typ. Max. 16 Unit MHz ns ns ns 20 ms
XTAL EXTAL XTAL EXTAL XTAL EXTAL EC EC TEX TX TEX TEX
tXL, tXH tCR, tCF tEH, tEL tER, tEF
fC
tsys + 2001
32.768
kHz
tTL, tTH tTR, tTF
s ms
tsys indicates three values according to the contents of the clock control register (CLC; 00FEH) upper 2 bits
(CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11")
Fig. 1. Clock timing
1/fc
EXTAL XTAL
VDD - 0.4V 0.4V
tXH
tCF
tXL
tCR
Fig. 2. Clock applied condition
Crystal oscillation Ceramic oscillation External clock 32kHz clock applied condition Crystal oscillation
EXTAL
XTAL
EXTAL
XTAL
TEX
TX
C1
C2
74HC04
C1
C2
Fig. 3. Event count clock timing
TEX EC 0.8VDD 0.2VDD
tEH tTH
tEF tTF
tEL tTL
tER tTR
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CXP888P60
(2) Serial transfer (CH0) Item CS0 SCK0 delay time CS0 SCK0 floating delay time CS0 SO0 delay time CS0 SO0 floating delay time CS0 high level width SCK0 cycle time SCK0 high and low level widths SI0 input set-up time (against SCK0 ) SI0 input hold time (against SCK0 ) SCK0 SO0 delay time Note 1) Symbol Pin SCK0
(Ta = -10 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Condition Chip select transfer mode (SCK0 = output mode) Chip select transfer mode (SCK0 = output mode) Chip select transfer mode Chip select transfer mode Chip select transfer mode Input mode SCK0 Output mode Input mode SCK0 Output mode SCK0 input mode SI0 SCK0 output mode SCK0 input mode SI0 SCK0 output mode SCK0 input mode SO0 SCK0 output mode Min. Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
tDCSK
tsys + 200 tsys + 200 tsys + 200 tsys + 200 tsys + 200
2tsys + 200 16000/fc
tDCSKF SCK0 tDCSO
SO0
tDCSOF SO0 tWHCS CS0 tKCY tKH tKL tSIK tKSI tKSO
tsys + 100
8000/fc - 50 100 200
tsys + 200
100
tsys + 200
100
ns ns
tsys indicates three values according to the contents of the clock control register (CLC; 00FEH) upper 2 bits (CPU clock selection). tsys [ns] = 2000/fc (Upper 2 bits = "00"), 4000/fc (Upper 2 bits = "01"), 16000/fc (Upper 2 bits = "11") Note 2) The load of SCK0 output mode and SO0 output delay time is 50pF + 1TTL.
- 19 -
CXP888P60
Fig. 4. Serial transfer timing (CH0)
tWHCS
0.8VDD CS0 0.2VDD
tKCY tDCSK tKL tKH tDCSKF
0.8VDD SCK0 0.2VDD
0.8VDD
tSIK
tKSI
0.8VDD SI0 Input data 0.2VDD
tDCSO
tKSO
tDCSOF
0.8VDD SO0 Output data 0.2VDD
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CXP888P60
Serial transfer (CH1) Item SCK1 cycle time SCK1 high and low level widths SI1 input set-up time (against SCK1 ) SI1 input hold time (against SCK1 ) SCK1 SO1 delay time Symbol Pin SCK1
(Ta = -10 to +75C, VDD = 4.5 to 5.5V, Vss = 0V) Condition Input mode Output mode SCK1 Input mode Output mode SI1 SCK1 input mode SCK1 output mode SI1 SCK1 input mode SCK1output mode SO1 SCK1 input mode SCK1 output mode Min. 1000 16000/fc 400 8000/fc - 50 100 200 200 100 200 100 Max. Unit ns ns ns ns ns ns ns ns ns ns
tKCY tKH tKL tSIK tKSI tKSO
Note) The load of SCK1 output mode and SO1 output delay time is 50pF + 1TTL.
Fig. 5. Serial transfer timing (CH1)
tKCY tKL tKH
0.8VDD SCK1 0.2VDD
tSIK
tKSI
0.8VDD SI1 Input data 0.2VDD
tKSO
0.8VDD SO1 0.2VDD Output data
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CXP888P60
(3) A/D converter characteristics (Ta = -10 to +75C, VDD = AVDD = 4.5 to 5.5V, AVREF = 4.0 to AVDD, Vss = AVss = 0V reference) Item Resolution Linearity error Absolute error Conversion time Sampling time Reference input voltage Analog input voltage
Only for A/D converter operation Ta = 25C VDD = AVDD = AVREF = 5.0V VDD = AVss = 0V
Symbol
Pin
Condition
Min.
Typ.
Max. 8 1 2
Unit Bits LSB LSB s s
tCONV tSAMP
VREF VIAN AVREF AN0 to AN7 Operation mode
160/fADC 1 12/fADC 1 AVDD - 0.5 0 0.6 AVDD AVREF 1.0 10
V V mA A
AVREF current
IREF
AVREF
SLEEP mode STOP mode 32kHz operation mode
Fig. 6. Definitions of A/D converter terms
FFH FEH
Digital conversion value
1) fADC indicates the below values due to the contents of bit 0 (ADCCK) of the ADC operation clock selection register (MSC: 01FFH), bits 7 (PCK1) and 6 (PCK0) of the clock control register (address: 00FEH).
Linearity error 01H 00H VZT Analog input VFT
ADCCK PCK1, PCK0 00 ( = fEX/2) 01 ( = fEX/4) 11 ( = fEX/16)
0 (/2 selection) fADC = fc/2 fADC = fc/4 fADC = fc/16
1 (selection) fADC = fc fADC = fc/2 fADC = fc/8
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CXP888P60
(4) Interruption, reset input (Ta = -10 to +75C, VDD = 4.5 to 5.5V, Vss = 0V reference) Item External interruption high and low level widths Reset input low level width Symbol Pin INT0 INT1 INT2 NMI RST Condition Min. Max. Unit
tIH tIL tRSL
1
s
32/fc
s
Fig. 7. Interruption input timing
tIH INT0 INT1 INT2 NMI (Falling edge) tIL
0.8VDD 0.2VDD
Fig. 8. Reset input timing
tRSL
RST 0.2VDD
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CXP888P60
Analog Circuit Characteristics (1) Amplifier circuit reference voltage characteristics (Ta = -10 to +75C, VDD = AMPVDD = 5.0V, Vss = AMPVSS = 0V reference) Item Reference level output voltage Symbol VOR Pin VREFOUT CTLAG VREFOUT Reference level output current IOR CTLAG VREFOUT = VREFOUT + 0.5V VREFOUT = VREFOUT - 0.5V CTLAG = CTLAG + 0.5V CTLAG = CTLAG - 0.5V Conditions Min. 2.2 2.15 3.50 -0.30 2.80 -0.30 Typ. 2.4 2.35 6.5 -0.85 5.5 -0.85 Max. 2.6 2.55 Unit V V mA mA mA mA
(2) CTL 1st amplifier characteristics (Ta = -10 to +75C, VDD = AMPVDD = 5.0V, Vss = AMPVSS = 0V, CTLAG reference) Item Symbol Pin Conditions Gain = 16dB RECCTL (-) = 0V Gain = 27dB RECCTL (-) = 0V AVCTL1 RECCTL (+) Gain = 42dB CTLFAMPO2 RECCTL (-) = 0V Gain = 58dB RECCTL (-) = 0V Offset voltage VOSCTL1 CTLAMP (+) Input resistance RINCTL1 CTLAMP (-) CTLAMP (+) Charge switch ON resistance RCCTL1 CTLAMP (-) CTLAMP (+) and CTLAMP (-) = open Charge switch OFF CTLAMP (+) = +0.2V Charge switch OFF CTLAMP (-) = +0.2V Charge switch ON CTLAMP (+) = +0.5V Charge switch ON CTLAMP (-) = +0.5V 315 315 Min. 12.5 23.5 39.0 54.5 -40 26.0 1.20 Typ. 14.5 25.5 41.5 57.0 0 44.5 2.0 560 560 400 400 250 250 1010 1010 770 770 310 310 Max. 16.5 27.5 44.0 59.5 +40 Unit dB dB dB dB mV k k
Voltage gain 1
RECCTL and CTLCIN connection RREAD switch ON resistance
RECCTL (+) During CTL read operation, CTLCIN (+) CTLCIN (+) - RECCTL (+) = 0.2V RECCTL (-) During CTL read operation, CTLCIN (-) CTLCIN (-) - RECCTL (-) = 0.2V CTLCIN (+) During CTL write operation, CTLCIN (+) = AMPVSS + 0.2V During CTL write operation, CTLCIN (-) = AMPVSS + 0.2V
CTLCIN 0V fix RWRITE switch ON resistance
CTLCIN (-)
1) When CTLCIN (+), CTLAMP (+) pins and CTLCIN (-), CTLAMP (-) pins are AC coupled, and then the signal is input from RECCTL (+) pin. 2) The result after measuring the CTLFAMPO output waveform or voltage gain. Note) The gain increases by approximately 1.5dB when the AC coupling capacitor (47F) is connected to CTLAMP (+) and CTLAMP (-) pins, and the signal is input from CTLAMP (+) and CTLAMP (-) pins. - 24 -
CXP888P60
(3) CTL 2nd amplifier characteristics (Ta = -10 to +75C, VDD = AMPVDD = 5.0V, Vss = AMPVSS = 0V, CTLAG reference) Item Symbol Pin Conditions Gain = 5dB Voltage gain1, 2 AVCTL2 Gain = 11dB Gain = 16dB Gain = 20dB LPF cut-off frequency 1, 2 Offset voltage 2 fCCTL VOSCTL2 fDC - 3dB CTLSAMPI = open Comparator level = +100mV0-p CTLSAMPI Comparator level = +250mV0-p Comparator level 2 VCCTL Comparator level = +400mV0-p Comparator level = -100mV0-p Comparator level = -250mV0-p Comparator level = -400mV0-p Input resistance Charge switch ON resistance RINCTL2 RCCTL2 Charge switch OFF CTLSAMPI = +0.2V Charge switch ON CTLSAMPI = +0.5V Min. 4.8 10.4 15.3 19.3 15.0 -50 70.0 215 370 -70.0 -220 -370 10.0 Typ. 5.8 11.5 16.5 20.5 25.0 0 100 245 400 -100 -250 -400 18.0 770 1140 Max. 6.8 12.6 17.7 21.7 40.0 +50 130 275 430 -130 -280 -430 Unit dB dB dB dB kHz mV mV0-p mV0-p mV0-p mV0-p mV0-p mV0-p k
1) When the signal is input with the AC coupling capacitor (47F) connected to CTLSAMPI pin. 2) The result after measuring the output waveform of amplifier internal low-pass filter or voltage value.
(4) CTLAMP characteristics (1st amplifier + 2nd amplifier) (Ta = -10 to +75C, VDD = AMPVDD = 5.0V, Vss = AMPVSS = 0V reference) Item Voltage gain 1 Input amplitude (peak value) Input sensitivity Input dead band Symbol AVCTL Pin Conditions CTL 1st amplifier gain = 16dB CTL 2nd amplifier gain = 20dB RECCTL (-) = 0V RECCTL (-) = 0V RECCTL (+) VSCTL VNSCTL CTL 1st amplifier gain = 58dB CTL 2nd amplifier gain = 20dB Comparator level = +400mV0-p -400mV0-p 0.015 RECCTL (-) = 0V 0.08 0.04 0.10 mV0-p mV0-p Min. 31.8 Typ. 35.0 Max. 38.2 Unit dB
VPKCTL
300
mV0-p
1) As for other combinations of the amplifier gains, CTL 1st amplifier and CTL 2nd amplifier are added respectively. Note) The result when the signal is input from RECCTL (+) pin with CTL 1st amplifier + CTL 2nd amplifier after performing AC coupling of CTLCIN (+), CTLAMP (+) pins and CTLCIN (-), CTLAMP (-) pins, and CTLFAMPO, CTLSAMPI pins.
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CXP888P60
(5) CFGAMP characteristics (Ta = -10 to +75C, VDD = AMPVDD = 5.0V, Vss = AMPVDD = 0V, VREFOUT reference) Item Symbol Pins Conditions Gain = 0dB Voltage gain 1, 2 AVCFG Gain = 20dB Gain = 34dB Gain = 38dB LPF cut-off frequency 1, 2 Offset voltage 2 Comparator judgment level width 2 fCCFG VOSCFG fDC - 3dB CFG = open Comparator schimitt width = 320mVp-p Comparator schimitt width = 160mVp-p Gain = 38dB Comparator level = 320mVp-p CFG Gain = 38dB Comparator level = 160mVp-p Gain = 38dB Comparator level = 320mVp-p Gain = 38dB Comparator level = 160mVp-p Input resistance Charge switch ON resistance RINCFG RCCFG Charge switch OFF CFG = +0.2V Charge switch ON CFG = +0.5V CFG = sine wave with 50% duty 48.0 3.40 1.50 5.5 Min. -0.3 19.2 33.2 37.0 30.0 -50 260 110 Typ. 0.6 20.8 34.8 38.7 55.0 0 320 155 4.20 2.10 4.10 2.00 8.3 455 50.0 710 52.0 2.4 Max. 2.2 22.4 36.4 40.4 80.0 +50 360 200 5.00 2.40 Unit dB dB dB dB kHz mV mVp-p mVp-p mVp-p mVp-p mVp-p mVp-p k % V0-p
VCCFG
Input sensitivity 1
VSCFG
Input dead band 1
VNSCFG
Digital output DTYCFG waveform duty 1, 3 Input amplitude (peak value) 1 VPKCFG
1) When the signal is input with the AC coupling capacitor (47F) connected to CFG pin. 2) The result after measuring the output waveform of amplifier internal low-pass filter or voltage value. 3) The result after measuring the digital signal waveform output from the amplifier circuit.
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CXP888P60
(6) DFGAMP characteristics (Ta = -10 to +75C, VDD = AMPVDD = 5.0V, Vss = AMPVSS = 0V, VREFOUT reference) Item Symbol Pins Conditions Gain = 0dB Voltage gain 1, 2 AVDFG Gain = 20dB Gain = 34dB Gain = 38dB LPF cut-off frequency 1, 2 Offset voltage 2 Comparator judgment level width 2 fCDFG VOSDFG fDC - 3dB DFG = open Comparator schmitt width = 320mVp-p VCDFG Comparator schmitt width = 160mVp-p Gain = 38dB Comparator level = 320mVp-p VSDFG DFG Gain = 38dB Comparator level = 160mVp-p Gain = 38dB Comparator level = 320mVp-p VNSDFG Gain = 38dB Comparator level = 160mVp-p Charge switch OFF DFG = +0.2V Charge switch ON DFG = +0.5V CFG = sine wave of 50% duty 48.0 3.40 1.50 5.5 Min. -0.3 19.2 33.2 37.0 30.0 -50 260 110 Typ. 0.6 20.8 34.8 38.7 55.0 0 320 155 4.20 2.10 4.10 2.00 8.3 455 50.0 710 52.0 2.4 Max. 2.2 22.4 36.4 40.4 80.0 +50 360 200 5.00 2.40 Unit dB dB dB dB kHz mV mVp-p mVp-p mVp-p mVp-p mVp-p mVp-p k % V0-p
Input sensitivity 1
Input dead band 1
Input resistance Charge switch ON resistance Digital output waveform duty 1, 3 Input amplitude (peak value) 1
RINDFG RCDFG DTYDFG VPKDFG
1) When the signal is input with the AC coupling capacitor (47F) connected to DFG pin. 2) The result after measuring the output waveform of amplifier internal low-pass filter or voltage value. 3) The result after measuring the digital signal waveform output from the amplifier circuit.
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CXP888P60
(7) DPGAMP characteristics (Ta = -10 to +75C, VDD = AMPVDD = 5.0V, Vss = AMPVSS = 0V, VREFOUT reference) Item Voltage gain 1, 2 LPF cut-off frequency 1, 2 Offset voltage 2 Symbol AVDPG fCDPG VOSDPG fDC - 3dB DFG = open Comparator level = 600mV0-p Comparator level = 400mV0-p Comparator level = 200mV0-p Comparator level 2 VCDPG Comparator level = 100mV0-p Comparator level = -600mV0-p Comparator level = -400mV0-p Comparator level = -200mV0-p Comparator level = -100mV0-p Comparator level = 600mV0-p, 200mV0-p Input sensitivity 1 Comparator level = 400mV0-p, 100mV0-p VSDPG DPG Comparator level = -600mV0-p, -200mV0-p Comparator level = -400mV0-p, -100mV0-p Comparator level = 600mV0-p, 200mV0-p Comparator level = 400mV0-p, 100mV0-p VNSDPG Comparator level = -600mV0-p, -200mV0-p Comparator level = -400mV0-p, -100mV0-p Input resistance Charge switch ON resistance Input amplitude (peak value) 1 RINDPG RCDPG VPKDPG Charge switch OFF DPG = +0.2V Charge switch ON DPG = +0.5V 113 70 -120 -80 24.0 Pins Conditions Min. 11.1 30.0 -35 570 370 175 72 -572 -368 -174 -71 Typ. 12.0 55.0 0 605 400 200 100 -605 -400 -200 -100 150 100 -155 -109 142 90 -150 -103 44.5 450 860 2.4 Max. 13.2 85.0 +35 640 432 220 125 -643 -438 -223 -124 180 120 -185 -130 Unit dB kHz mV mV0-p mV0-p mV0-p mV0-p mV0-p mV0-p mV0-p mV0-p mV0-p mV0-p mV0-p mV0-p mV0-p mV0-p mV0-p mV0-p k V
Input dead band 1
1) When the signal is input with the AC coupling capacitor (47F) connected to DPG pin. 2) The result after measuring the output waveform of amplifier internal low-pass filter or voltage value.
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CXP888P60
(8) CTL write circuit characteristics (Ta = -10 to +75C, VDD = AMPVDD = 5.0V, Vss = AMPVSS = 0V reference) Item Output resistance Symbol ROH ROL RECCAP Pins Conditions RECCAP = AMPVDD - 0.5V RECCAP = AMPVDD + 0.5V Write current = 2.0mA Write current = 2.5mA Write current = 3.0mA Output current 1 IOREC Write current = 3.5mA RECCTL (+) RECCTL (-) Write current = 4.0mA Write current = 4.5mA Write current = 5.0mA Write current = 5.5mA Write current = 6.0mA Min. 450 410 1.3 1.7 2.1 2.6 2.9 3.3 3.7 4.0 4.4 Typ. 625 555 2.0 2.5 3.1 3.6 4.0 4.6 5.1 5.6 6.1 Max. 1005 840 2.9 3.7 4.5 5.2 5.9 6.6 7.2 8.0 8.9 Unit mA mA mA mA mA mA mA mA mA
1) The current value which flows when RECCTL (+) pin and RECCTL (-) pin are shorted.
(9) Amplifier operating current characteristics (Ta = -10 to +75C, VDD = AMPVDD = 5.0V, Vss = AMPVSS = 0V reference) Item Amplifier operating current Symbol IAMP Pins AMPVDD Conditions When the amplifier is operating 1 When the amplifier is not operating Min. Typ. 7.6 Max. 12.0 10 Unit mA A
1) The CTL recording current is added during CTL write. Note) The amplifier operation and NOT-operation is controlled according to the contents of amplifier power supply control register (ASWC: 05E2H) bits 5, 4, 1 and 0.
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CXP888P60
Supplement Fig. 9. Recommended oscillation circuit
(i) (ii)
EXTAL
XTAL Rd
TEX
TX Rd
C1
C2
C1
C2
Manufacturer
Model
fc (MHz) 8.00
C1 (pF) 10
C2 (pF) 10
Rd ()
Circuit example
RIVER ELETEC CO., LTD.
HC-49/U03
10.00 12.00 16.00 8.00 16 (12) 16 (12) 12 12 30 16 (12) 16 (12) 12 12 18 5 5
0
(i)
KINSEKI LTD.
HC-49/U (-S)
10.00 12.00 16.00
0
(i)
P3
32.768kHz
470k
(ii)
Mask option table Item Reset pin pull-up resistor Input circuit format1 Mask product Existent/Non-existent CMOS schmitt/ TTL schmitt Existent (CXP88616/24) Non-existent (CXP88732/40/48, CXP88852/60) CXP888P60Q-1Existent TTL schmitt CXO888P60Q-2Existent TTL schmitt
Power-on-reset circuit
Non-existent
Existent
1) The input circuit format can be selected for PE3/SYNC pin.
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CXP888P60
Characteristics Curve
IDD vs. VDD
(fc = 16MHz, Ta = 25C, Typical) 100 1/2 dividing mode 1/4 dividing mode 10 30 35
IDD vs. fc
(VDD = 5.0V, Ta = 25C, Typical)
1/2 dividing mode
IDD - Supply current [mA]
1/16 dividing mode SLEEP mode 25
1 32kHz mode 0.1 32kHz SLEEP mode 0.01 2 3 4 5 6
IDD - Supply current [mA]
20 1/4 dividing mode 15
10 1/16 dividing mode 5 SLEEP mode 0 5 10 15 16 20 fc - System clock [MHz]
VDD - Supply voltage [V]
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CXP888P60
Package Outline
Unit: mm
100PIN QFP (PLASTIC)
23.9 0.4 + 0.4 20.0 - 0.1 80 51 + 0.1 0.15 - 0.05
81
50
+ 0.4 14.0 - 0.1 17.9 0.4
15.8 0.4
A 100 31
1
0.65
+ 0.15 0.3 - 0.1
30 0.13 M + 0.35 2.75 - 0.15
+ 0.2 0.1 - 0.05
0.15
DETAIL A
0.8 0.2
0 to 10
(16.3)
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-100P-L01 QFP100-P-1420 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING 42/COPPER ALLOY 1.7g
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